This page is intended to provide an explanation of some of the various types of instruction sets. The instruction sets are listed starting with the simplest and ending with the most complex ...
Architectural conformance and implementation verification are necessary but different for RISC-V designs, yet few verification engineers have experience on the conformance side. While RISC-V enables ...
RISC-V pioneer SiFive has signed a deal with Nvidia to incorporate Nvidia NVLink Fusion into its data center products. The agreement means that SiFive will be able to connect its RISC-V CPUs to Nvidia ...
Bao Yungang, vice director of the Chinese Academy of Sciences' Institute of Computing Technology and chief scientist at the Beijing Open Source Chip Academy, predicts RISC-V will become the world's ...
目前,业界对此尚有争论,但从市场表现来看,x86服务器仍是首选。赛迪顾问在刚刚发布的《2023-2024年中国服务器市场研究年度报告》就提到,x86服务器依旧占据主力市场,且未来三年市场规模保持增长,预计到2026年市场规模突破1600亿元。
The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems ...
The adoption of RISC-V with open standards in automotive applications continues to accelerate, leveraging its flexibility and scalability, particularly benefiting the automotive industry’s shift to ...
Forbes contributors publish independent expert analyses and insights. Dave Altavilla is a Tech Analyst covering chips, compute and AI. For decades, chip architectures have been dominated by a pair of ...
Old-timers might recall the idea of "RISC" as a once-upon-a-time processor design ideology. RISC processors were mostly used for servers from Sun Microsystems, DEC, and other companies of a bygone era ...
What just happened? Since its introduction in 2006, CUDA has been a proprietary technology running exclusively on Nvidia's own GPU hardware. Now, the GeForce maker appears ready to open CUDA to at ...
Many features will have to rely on the PCIe interfaces, and for instance, the Titan motherboard also offers four USB 3.0 ports, which must have been implemented through a PCIe to USB 3.0 bridge. It ...